This invention relates to a voltage switching circuit in an integrated circuit (IC) electrically-programable-read-only memory (EPROM) or the like and more particularly to such a switching circuit for connecting a row/column-select supply line to either a high-voltage source (V.sub.pp) or a low voltage source (V.sub.DD).
EPROM devices are usually comprised of an array of floating gate metal oxide semiconductor (MOS) transistors, as are other programable memory array devices. The programing of such arrays entails applying a high voltage to row/column-select and bit lines whereas reading is accomplished by applying a relatively low voltage to row/column-select and bit lines. An EPROM of this kind is described by A. Owens, M. Halfacre and D. Pan in the U.S. patent application Ser. No. 680,198 filed Dec. 10, 1984 and assigned to the same assignee as is the present invention.
It is standard practice to make EPROM and other programable arrays in P-type material wherein N-channel transistors may be simply formed by adding N-type source and drain regions therein. In such EPROM IC chips, the switch circuit for alternately connecting a high and low voltage source to a row/column-select supply line employs two series-connected N-channel transistors between the high and low voltage sources with the junction between them being connected to the row/column-select supply line. Switch control circuitry turns on one of the series connected N-channel transistors when the other is off and vice versa, all in response to a binary logic control signal.
The prior art switch employing a pair of series connected N-channel transistors has the disadvantage that the transistor connected to either voltage source, when rendered conducting, necessarily inserts a voltage drop in the connection between the voltage source and the row/column-select line which is equal to or greater than the characteristic threshold voltage of that transistor. That voltage drop leads to reduced voltage and limited switching speed.
It is an object of the present invention to overcome the above-noted shortcomings of row/column-select supply switching circuits in electrically-programable floating-gate-transistor arrays.
It is also an object of this invention to provide in an integrated circuit array, an FET circuit for alternately connecting to a row/column-select supply bus a source of high supply voltage and a source of low supply voltage without a transistor-threshold drop therebetween.
It is a further object of this invention to provide such an FET circuit that itself is powered from said high and low supply voltage sources.
It is yet a further object of this invention to provide such an FET circuit which connects the row/column-select supply bus to the high and low supply sources, in response to the application at the input of the circuit of a low level logic signal of one kind and the other kind, respectively.